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E2U0024-16-X2
Semiconductor MSM7503
Semiconductor Multi-Function PCM CODEC
This version: Jan. 1998 MSM7503 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7503 is a high performance, low power CODEC LSI device integrating a 2-wire time division transmission (ping-pong transmission) interface function and has a basic function of man-machine interface to that of the MSM7502. The MSM7503 operates from single 5 V power supply and is ideal for digital telephone terminals such as pushbutton telephone sets and digital PBXs. The MSM7503 ping-pong transmission interface supports a bidirectional communication of up to 800 m long on the 2-wire twisted pair line, and can send and receive voice data at 64 kbps and control data at 16 kbps. The man-machine interface consists of analog speech path, key-scanner, tone generators, CODEC meeting the m/A companding law, and processor interface, which are controlled via 8bit data buses.
FEATURES
* Single +5 V Power Supply * Low Power Dissipation Power ON Mode Power Down Mode * Pin-Pong Transmission
: 50 mW Typ. 100 mW Max. : 15 mW Typ. 30 mW Max. : Burst of 8 kHz, Transmission of 256 kbps, AMI coding, 2-wire time division transmission * Transmission data configuration : Transmit Start bit (1 bit), K-bit (1 bit), Control bit (2 bits), Voice bit (8 bits), DC balance bit (1 bit), totalling 13 bits Receive Sync bit (4 bits), K-bit (1 bit), Control bit (2 bits), Voice bit (8 bits), DC balance bit (1 bit), totalling 16 bits * Control Data Interface supports synchronous and asynchronous communications * Built-in Power-on Reset by the power supply voltage monitoring * Output of the ping-pong transmission monitoring signal * CODEC complied by the ITU-T companding law * Calling Tone Interval : Controlled by processor * Calling Tone Combination : Controlled by processor, 6 modes * Calling Tone Volume : Controlled by processor, 4 modes * Ringing Tone Interval : Controlled by processor * Ringing Tone Frequency : Controlled by processor, 6 modes * Ringing Tone Level : Controlled by processor, 4 levels * Built-in PB Tone Generator * Built-in Speech path Control Switches * General Latch Output for External Control : 2 bits * Watch-dog Timer : 500 ms
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Semiconductor * Scanning I/O Output : 8 bits Input : 8 bits * Direct Connection to Handset : 1.2 kW driving available * Built-in Pre-amplifier for Loud-speaker * Hand-free Interface * m-law/A-law Switchable CODEC * LCD Deflection Angle Voltage : Controlled by processor, 8 levels * Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7503GS-BK)
MSM7503
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Semiconductor
MSM7503
BLOCK DIAGRAM
Communication Suppervisor R1N R2N I/O CLK Start-Stop Sampling T * Counter
PS SYNC CLK1 CLK2 CLK3 CLC FHW FD FK BHW BD BDS CTEST
Start bit Detector R * Mix Transmit Polarity Definition
T1N T2N XOUT X1 X2 TEST Voltage Detect MPAO MPAI TPAO TPAI MPBO MPBI TPBI MLDYI CAO R1I R2I RPO RMI RMO0 RMO1 SPI 0 dB SW10 VOL6 SW9
T * Mix
Crystal Oscillator Reset WDT Output 1024 kHz VOL9 + 20 dB VOL8 + + AIN PCMOUT SW1 SW2 SW7 SW16 DIV VOL1 VOL2 -8.7 dB 0 dB VOL7 SW5 0 dB -3 dB -6.8 dB VOL5 0 dB VOL11 VOL12 SW6 SW8 SW18 SW21 SW15 SW11 SW20 SW3 SW4 SW17 SW14 SW13 SW5 64 kHz PB GEN. R Tone GEN. 400 425 440 450 400 16 400 20 F Tone GEN. 1 kHz S Tone GEN. Latch 8 kHz WRN RDN CEN Processor INTF DB0 to DB7 AD0 AD1 LA LB VLCD GEN. Man-machine INTF Scanning Output Scanning Input VLCD 0 dB 5.7 dB VOL3 VOL4 m/A CODEC SW12 TO CAI
-
I/O INTF
LRSTN
VOL10 0 dB
-
AOUT PCMIN
-
SPO
-
SA0
VOL13
SW19 SG GEN.
VA
VD
AG
DG
SGT SGC
PO0~PO7
PI0~PI7
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Semiconductor
MSM7503
PIN CONFIGURATION (TOP VIEW)
69 XOUT 77 CLK3 68 TEST 70 BDS 72 R2N 71 R1N 78 CLC 74 T2N 73 T1N
76 BD
CLK2 1 CLK1 2 SYNC 3 FHW 4 BHW 5 CTEST 6 LRSTN 7 LB 8 LA 9 SAO 10 VLCD 11 DG 12 AG 13 RMO1 14 RMO0 15 RMI 16 SPI 17 SPO 18 RPO 19 R2I 20 R1I 21 MLDYI 22 MPBO 23 MPBI 24
MPAO 25 MPAI 26 TPBI 27 TPAO 28 TPAI 29 SGT 30 TO 31 VA 32 CAI 33 SGC 34 CAO 35 PO7 36 PO6 37 PO5 38 PO4 39 PO3 40
65 VD
75 PS
67 X2
66 X1
80 FD
79 FK
64 CEN 63 RDN 62 WRN 61 AD1 60 AD0 59 DB7 58 DB6 57 DB5 56 DB4 55 DB3 54 DB2 53 DB1 52 DB0 51 PI7 50 PI6 49 PI5 48 PI4 47 PI3 46 PI2 45 PI1 44 PI0 43 PO0 42 PO1 41 PO2
80-Pin Plastic QFP
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Semiconductor
MSM7503
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB General latch outputs for external control. Statuses of these outputs are controlled via the processor interface. Refer to the description of the control data for details. These outputs provide the capability to drive one TTL.
DG Digital Ground. DG is separated from the analog ground AG inside the device. But, DG should be connected as close to the AG pin on PCB as possible.
AG Analog Ground.
SA0 Sounder (calling tone) driving outputs. Through processor control, the calling tone volume is selectable from 4 levels and one of six tone combinations is selectable. Initially, the calling tone volume is set at a maximum and the tone combination is set at a 16 Hz Wamble tone by a combination of 1 kHz and 1.3 kHz. The SA0 outputs pulse waveforms using DG as a reference potential.
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Semiconductor
MSM7503
RMI, RMO0, RMO1 Receive main amplifier input and outputs. RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier. The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a handset is directly connected between RMO0 and RMO1. During the system power down, the RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is determined by a resistor connected between RPO and RMI, and a resistor connected between RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezoreceiver with an impedance greater than 1.2 kW is available. If the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech path is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO R1
RMI C1
RMO0 R2
C2 Main amplifier gain without capacitors G= R2 R1
SPI Addition input of speaker amplifier. The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a gain between 0 dB and -18 dB in a 6 dB step, or a gain between 0 dB and -28 dB in a 4 dB step through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by gain setting).
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Semiconductor SPO
MSM7503
Output of pre-amplifier for speaker. Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker. During the whole system power down mode, SPO is at an analog ground level. During the whole system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone, F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from the speaker by processor control. When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the CAO pin for CODEC output is internally connected.
R1I, R2I, RPO R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier. Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is used as the mixing signal input pin. The typical gain between R1I and PRO is -6 dB. Through processor control, gains are variable from -14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of -9, -6, -3, or 0 dB. The gain between R2I and RPO is fixed to 0 dB. During the whole system power-on mode, the RPO output is in non-signal state, and speech signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control. During the whole system power-down mode, the RPO output is the analog ground level. The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The input resistance of R2I is typically 20 kW. MLDYI Hold tone signal input. For example, the output of external melody IC is connected to this pin. Through processor control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The typical gain between MLDYI and TO is -2 dB. Through processor control, a gain between -2 dB and -11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is -3 dB. Through processor control, a gain between -3 dB to -31 dB is also settable at 4 dB steps. MLDYI is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.
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Semiconductor
MSM7503
TPBI, TO TPBI is the input and TO is the output of the transmit pre-amplifier (B). When the handset is used, TPBI is connected to the transmit pre-amplifier (A) output pin (TPAO). If adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between TPAO and TPBI. Through processor control, the signal applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin. During the whole system power down mode, TO is at an analog ground level. The typical gain between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7 dB is also settable at 3 dB steps. The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between -9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW resistor between TPBI and SGT.
A circuit example for adjustment of frequency characteristics
TPAO R3 C4
TPBI C3
SGT
R4
MPAI, MPAO Handfree microphone pre-amplifier (A) input and output. MPAI is the input and MPAO is the output. The speech path between MPAI and MPAO is always active regardless of processor control. During the whole system power saving mode, MPAO is at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance input, so insert an about 100 kW between MPAI and SGT.
MPBI, MPBO The handfree microphone (B) input and output. MPBI is the inverted input and MPBO is the output. With an external resistor, the amplifier gain is adjusted in the range between -25 dB and +25 dB. A signal on the MPBO is output via the TO pin through processor control. During the whole system power down mode, MPBO is at an analog ground level. The gain between MPBO and TO is fixed to 0 dB.
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Semiconductor TPAI, TPAO
MSM7503
The transmit pre-amplifier (A) input and output. TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit path from TPAI to TPAO is always active regardless of processor control. During the whole system power down mode, TPAO is at an analog ground level. The gain between TPAI and TPAO is fixed to 20 dB.
SGT Transmit path signal ground. SGT outputs half the supply voltage. During the whole power down mode, SGT output is in a high impedance state.
SGC Bypass capacitor connecting pin for a signal ground level. Insert a 0.1 mF high performance capacitor between SGC and AG.
VA, VD +5 V power supply. VA is for an analog circuit and VD is for a digital circuit. Both VA and VD should be connected to the +5 V analog path of the system.
CAI, CAO CODEC analog input and output. CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an about 100 kW bias resistor between CAI and SGT. CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling capacitor. A bias resistor is not required to R1I. During the whole system or CODEC power down mode, CAO is at the SG voltage level.
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Semiconductor PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
MSM7503
Scanning outputs. These output pins need external pull-up resistors because of their open- drain circuits. But, when these are used in combination with PI0 to PI7, pull-up resistors are not required. Through processor control, these outputs can be set open or to digital "0". Initially, these outputs are set at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7 Scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7). Since these inputs are pulled up inside the IC, external resistors are not required.
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7 Data bus I/O pins. These pins are configured as an output during the READ mode only and as an input during other modes.
T1N, T2N Line transmit signal output. Signals which consist of a total of 13 bits configured by the start bit (fixed at "1"), the K bit (fixed at "1"), the D bits (control data of two bits), the transmit B bits (eight for voice and data) and the DC bit (1 bit for the DC balance) at the bit rate of 256 kHz are output in burst mode from the T1N pin and the T2N pin in turn at intervals of 125 msec. These output signals become the AMI code with a duty of 50% in the line coding configuration by connecting to the line via a transformer etc. In the output timing of the T1N and T2N pins, the top bit of the signal is output after receiving a 16-bit signal.
R1N, R2N Line receive signal input. Line signals (50% duty AMI code) which consist of a total of 16 bits configured by the frame synchronous bits (four bits with "1"), the K bit (one bit for polling), the D bits (control data of two bits), the receive B bits (eight bits for voice and data), and the DC bit (bit for DC balance) have been transmitted in burst mode at the bit rate of 256 kHz at interval of 125 msec. These signals should be input in the R1N pin and the R2N pin after separating then into the polarity of "+" and "-".
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Semiconductor SYNC
MSM7503
Synchronous signal (8 kHz) output. This synchronous signal is generated by dividing the oscillator output of 8.192 MHz, applying the frame synchronous bit included in the line signal as a reference phase. This signal also sent to the tone generator and the CODEC inside the device. All timing signals of the CODEC are synchronized by this signal.
CLK1 64 kHz CLK signal output synchronized to the SYNC signal output. This signal is connected to the CODEC inside the device and is used as a bit clock for receiving and sending the PCM I/O data from and to the ping-pong transmission interface. When an external signal is input to the BHW pin, or when the FHW pin outputs signals for the external circuit, the timing should be set by the CLK1 signal. This signal is always output in the power ON mode.
CLK2 16 kHz CLK signal output synchronized to the SYNC signal output. This signal can be used for the input or output of the control signal (BD input or FD output) of 16 kbps. This signal is always output in the power ON mode.
CLK3 CLK signal output of 256 kHz synchronized to the SYNC signal. This signal can be used when the control signal of 16 kHz is input or output from or to the external device by the start-stop synchronization. This signal is always output in the power ON mode.
CLC Control signal input for phase-inverting the 256 kHz CLK signal which is output form the CLK3 pin. If the reference phase is set by setting CLC to "0", the CLK signal of 256 kHz is phase-inverted against the reference phase by setting CLC to "1".
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Semiconductor FHW
MSM7503
The output of the extracted B-bit (8-bit sequence) from receive signals which are input to R1N and R2N. This signal is output synchronizing to the rising edge of a CLK1 (64 kHz) output signal beginning with the rising edge of a SYNC output signal. Since this pin is connected to the D/A converter of the CODEC inside device, the B bits of receive signals are decoded to analog signals.
BHW Input to the B bit slot of line signals transmitted from the T1N and T2N pins. The input signal to this pin must be synchronized to the CLK1 output signal (64 kHz) beginning with the rising edge of the SYNC output signal. The input signal is shifted at the falling edge of CLK1. In the case of inserting the voice data into the transmit B bit, the PCM output of the CODEC is connected to this input pin, and inserting the voice data into the B bit slot is enabled by setting SW12 to ON through processor control. In this case the BHW pin is used as an output pin, so external signals can not be input to this pin. This is an input and output pin of an open drain type with a pulled-up resistance of 5 kW.
FD The signal output of the extracted Control bit (2-bit sequence at 16 kbps) from line signals which are input to the R1N and R2N pins. This signal is output synchronizing to the rising edge of a CLK2 output signal beginning with the rising edge of the SYNC output signal. FD is an output pin of an open drain type with a pulled-up resistance of about 10 kW.
FK The signal output of the extracted K bit (8 kbps) from the line receive signals which are input to the R1N and R2N pins. This signal is output synchronizing to the rising edge of a SYNC output signal. FK is an output pin of an open drain type with a pulled-up resistance of about 10 kW.
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Semiconductor
MSM7503
BD Input to the D bit (2-bit sequence at 16 kbps) of line signals transmitted from the T1N and T2N pins. When the BDS control pin is in "0", this pin enters the synchronous mode and data must be input to this pin synchronizing with CLK2 (16 kHz). When the BDS control pin is set to "1", this pin enters the asynchronous data input mode and the asynchronous data of 11 bits including the start bit and stop bit can be input at data rate of 16 kbps.
BDS Control signal input for selection of the synchronous mode or asynchronous mode for control data (D-bit) input. When being at "0" level, this pin enters the synchronous data input mode, when being at "1" level, this pin enters the asynchronous data input mode.
PS Monitoring signal output for the state of the ping-pong transmission. When frames are synchronized (in normal operation) after receiving more than three consecutive frame synchronous signals which are included in the line receive signal sequence, this pin outputs "1". Otherwise, this pin outputs "0". PS is an output of an open drain type with pulled-up resistance of about 10 kW.
X1, X2 CLK oscillator circuit input and output. X1 is input and X2 is output. A crystal oscillator of 8.192 MHz should be connected between X1 and X2. If the frequency deviation in CLK oscillation is great with respect to the receive data rate, the noise of the CODEC increases. The oscillation frequency deviation in CLK should be kept in 20 ppm or less.
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Semiconductor XOUT
MSM7503
8.192 MHz CLK signal output. If capacitance load is given to the output, the current consumption will increase. About 0.03 mA/ pF. AD0, AD1 Address data inputs for the internal control registers. Addressing of the internal control registers is executed by AD0 and AD1 and sub address data, DB7 and DB6.
AD1 AD0 DB7 DB6 0 0 0 0 1 1 0 WRITE 0 1 0 1 1 1 1 1 1 1 READ 1 0 1 1 1 1 0 -- 0 0 1 1 -- 0 1 0 1 0 1 0 1 -- 0 1 0 1 -- Function ON/OFF controls of sounder, R-Tone, F-Tone Level/Frequency controls of sounder, R-Tone PB tone control Controls of internal speech path switch and general latch Watchdog timer reset Controls of receive gain and side tone gain Controls of transmit hold tone, PB tone, handfree input, handset inputs gain Controls of speaker pre-amplifier gain and additional speaker gain Controls of receive PAD and incoming tone input gain Scanning output control Scanning interrupt reset LCD deflection angle control voltage setting Power ON/OFF control CODEC control (Controls of companding law and digital loop) Scanning data read-out
WRN Write signal for internal control registers. Data on the data bus is written into the registers at the rising edge of WRN under the condition of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.
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Semiconductor RDN
MSM7503
Read signal input to read PI0 to PI7 out of the processor. When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
CEN Chip Enable signal input. When CEN is in digital "0" state, WRN and RDN are valid.
VLCD By processor control, VLCD outputs a DC voltage between 0 and 1.4 V is about 0.2 V step. This is used to control the deflection angle of the LCD display. VLCD has the internal resistance value of about 1 kW, so the external load of over 100 kW should be used. During initialized state, VLCD outputs the voltage of 0 V.
LRSTN Reset signal output for external circuit. This reset signal output pin goes to "0" level when the power supply is approximately more than 4.0 V or when the TEST pin is at digital "0" level and the watchdog timer (WDT) outputs a signal. The WDT output does not affect the LSRTN output when TEST pin is at digital "1" level. The LRSTN signal is also used as a reset signal for internal registers. When LRSTN is at "0" level, all internal control registers are initialized. The internal WDT outputs a 500 ms cycle signal when the LRSTN is at digital "1" and the processor does not send a timer reset signal. Refer to the figure 1 for the output timing of this output.
TEST Control signal input for deciding valid/invalid of reset control from the internal WDT output. When this input pin is at digital "0" level, the LRSTN output goes to "0" level. When this input pin is at "1" level, the internal WDT does not affect the LSRTN output.
CTEST Test pin for shipment testing. This pin should be set to "0" level.
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Semiconductor
MSM7503
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition AG, DG = 0 V AG, DG = 0 V AG, DG = 0 V -- Rating 0 to 7 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to 150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Range Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Symbol VD Ta VIH VIL tIr tIf RDL CDL Condition VA, VD (Voltage must be fixed) -- All Digital Input Pins All Digital Input Pins All Digital Input Pins All Digital Input Pins PO0 to PO7 PO0 to PO7 Other digital output pins except PO0 to PO7 25C 3C Min. 4.75 -10 2.2 0 -- -- 10 -- -- -- -50 -50 -- -- Typ. 5.0 25 -- -- -- -- -- -- -- 8.192 -- -- -- 16 Max. 5.25 70 VDD 0.8 50 50 -- 100 10 -- 50 50 80 -- Unit V C V V ns ns kW pF MHz ppm ppm W pF
Crystal Oscillator
Oscillating Frequency Allowable Frequency Deviation Temperature Characteristics Equivalent Series Resistance Production Load Capacitance
Recommend Operating Conditions (Analog Interface)
Parameter Symbol Condition TPAO, MPAO, MPBO, TO, Analog Load Resistance RAL RPO, SPO, CAO RMO0, RMO1 with respected to SG Level Analog Load Capacitance CAL TPAO, MPAO, MPBO, TO, RPO, SPO, CAO RMO0, RMO1 TPAI, TPBI, MPAI Allowable Analog Input Offset Voltage Voff MLDY R1I, R2I, SPI CAI With respect to SG Min. 20 0.6 -- -- -10 -50 -25 -100 Typ. -- -- -- -- -- -- -- -- Max. -- kW -- 30 70 10 50 25 100 mV pF nF Unit
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Semiconductor Recommended Operating Conditions (Processor Digital Interface)
Parameter Write Pulse Period Write Pulse Width Read Pulse Width Address Data Setup Time Address Data Hold Time CEN Setup Time CEN Hold Time Data Setup Time Data Hold Time Symbol PW TW TR tAW1 tAR1 tAW2 tAR2 tCW1 tCR1 tCW2 tCR2 tDW1 tDW2 Condition WRN WRN RDN AD0, AD1AEWRN AD0, AD1AERDN WRNAEAD0, AD1 RDNAEAD0, AD1 CENAEWRN CENAERDN WRNAECEN RDNAECEN DB0 to 7AEWRN WRNAEDB0 to 7 See Fig.2 Min. 2000 100 200 80 80 50 50 80 80 50 50 110 20 Typ. -- -- -- -- -- -- -- -- -- -- -- -- --
MSM7503
Max. -- -- -- -- -- -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Recommended Operating Conditions (Ping-Pong transmission Interface)
Parameter B Signal Set-up Time B Signal Hold Time D Signal Set-up Time D Signal Hold Time Receive Data Cycle Time Receive Data Width Receive Flame Cycle Time Symbol TSBHW THBHW TSBD THBD TCB TWB TFM Condition BHW Input BHW Input BD Input BD Input R1N, R2N Width of "L" at R1N and R2N -- See Fig. 3 See Fig. 3 See Fig. 4 See Fig. 4 See Fig. 5 See Fig. 5 See Fig. 5 Min. 50 50 50 50 -- 1.35 -- Typ. -- -- -- -- 3.906 1.953 125 Max. -- -- -- -- -- 2.5 -- Unit ns ns ns ns ms ms ms
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Semiconductor
MSM7503
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Power Supply Current Power Supply Voltage Detection Power Supply Voltage Non-Detection Input High Voltage Input Low Voltage High Input Leakage Current Low Input Leakage Current Digital Output High Voltage Digital Output Low Voltage Digital Output Leakage Current Analog Output Offset Voltage Input Capacitance Symbol IDD1 IDD2 IDD3 Vth Vtl VIH VIL IIH IIL Condition Operating Mode (No Signal, Sounder OFF) Whole system Power Down CODEC Power Down Power Supply Voltage at LRSTN = 1, See Fig. 1 Power Supply Voltage at LRSTN = 0, See Fig. 1 -- -- Digital Pins except for PI0 to PI7 PI0 to PI7 (Internal Pull-up Pins) Digital Pins except for PI0 to PI7 PI0 to PI7 (Internal Pull-up Pins) Output Pins 1 *1 IOH = 0.1 mA VOH Output Pins 2 *2 IOH = 1.6 mA All Output Pins IOH = 1 mA VOL IO Voff CIN RIN IOL = -1.6 mA DB0 to DB7 (Write Mode) TPAO, MPAO MPBO, TO, CAO, RPO, RMO0, RMO1, SPO -- TPAI, TPBI, MLDYI, RMI, MPAI, MPBI R1I, R2I, SPI CAI (fin : < 4 kHz) SG Voltage SG Drive Current Equivalent Pull-up Resistance -- ISGF ISGS RPULL -- FORCE Current SINK Current PI0 to PI7, VI = 0 V Min. -- -- -- 3.9 -- 2.2 0.0 -- -- -- 10 2.4 2.4 3.8 0.0 -- -200 -100 -- -- 10 -- VA/2 -0.05 1.0 0.3 200 Typ. 10 3 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 10 -- 1 VA/2 1.5 0.5 370 Max. 20 6 14 -- 3.8 VDD 0.8 2.0 2.0 0.5 25 VDD VDD VPP 0.4 10 200 100 -- -- -- -- VA/2 +0.05 -- -- 500 V mA mV pF MW kW MW V mA kW V Unit mA mA mA V V V V mA mA mA mA
Analog Input Resistance
Notes:
*1 BHW, FK, FD, PS *2 SYNC, CLK1, CLK2, CLK3, T1N, T2N, XOUT, LA, LB, LRSTN, DB0 TO DB7
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Semiconductor Digital Interface Characteristics
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Digital Output (Latch) Delay Time Key Scanning Output Delay Time Digital Output (Data) Delay Time Delay Time of Power Supply Voltage Detect Delay Time of LRSTN due to WDT Symbol tpd LA tpd scn tpd data tdRST1 tdRST2 TWDT tdRST3 tWRST tdSCK1 CLK Output Delay Time B Signal Delay Time D Signal Output Delay Time K Signal Output Delay Time SYNC Output Frequency SYNC Output Width CLK1 Output Frequency CLK2 Output Frequency CLK3 Output Frequency CLK Output Duty Ratio Line Output Signal Width Clock Output Jitter Width tsSCK2 tdSCK3 tdFHW tdFD tdFK fSYNC TWSYNC fCLK1 fCLK2 fCLK3 -- tWF CLK1, CLK2, CLK3 T1N, T2N "L" Width See Fig. 5 SYNC, CLK1, CLK2 CLK3 When use Xtal SYNCAECLK1 SYNCAECLK2 SYNCAECLK3 CLK1AEFHW CLK2AEFD See Fig. 3 See Fig. 4 See Fig. 3 See Fig. 4 See Fig. 4 LAEH HAEL LAEH HAEL See Fig. 1 Condition WRAELA, LB Pull-up resistance 10 kW RDAEDB0~DB7 LRSTN 0AE1 LRSTN 1AE0 See Fig. 2 See Fig. 2 WRAEPO0 to PO7 Min. 0.2 0.2 10 -- -- -- -- -- 366 366 366 -- -- -- -- -- -- -- -- -- -- -- -- -- Typ. -- -- 20 128 0.01 500 0.85 1.7 -- -- -- 10 340 10 740 500 8 16.6 64 16 256 50 1.953 250 Max. 1.5 1.5 100 -- -- -- -- -- 488 488 488 -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns kHz ms kHz kHz kHz % ms ns ns Unit ms ms ns ms ms ms ms
See Fig. 2 See Fig. 1
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Semiconductor AC Characteristics 1 (CODEC)
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Symbol Freq. Level (Hz) (dBm0) Loss T1 60 Loss T2 300 Loss T3 1020 0 Loss T4 2020 Loss T5 3000 Loss T6 3400 Loss R1 300 Loss R2 1020 0 Loss R3 2020 Loss R4 3000 Loss R5 3400 SD T1 3 SD T2 0 SD T3 1020 -30 SD T4 -40 SD T5 -45 SD R1 3 SD R2 0 1020 SD R3 -30 -40 SD R4 -45 SD R5 3 GT T1 -10 GT T2 1020 -40 GT T3 -50 GT T4 -55 GT T5 3 GT R1 -10 GT R2 1020 -40 GT R3 -50 GT R4 -55 GT R5 Nidle T Idle Channel Noise Nidle R Absolute Amplitude Absolute Delay Time AV T AV R Td -- 1020 1020 -- 0 0 -- -- Condition Min. 20 -0.20 -0.15 -0.15 0.0 -0.15 -0.15 -0.15 0.0 35 35 35 29 24 37 37 37 30 25 -0.3 -0.3 -0.5 -1.2 -0.3 -0.3 -0.5 -1.2 AIN = SG *1 *1 *2 CAI AE BHW FHW AE CAO CAI AE CAO BCLOCK = 64 kHz m A -- -- -- 0.5671 0.5671 -- Typ. 27 0.07 Reference -0.03 0.06 0.38 -0.03 Reference -0.02 0.15 0.56 43.0 41.0 38.0 31.0 26.5 43.0 41.0 40.0 34.0 31.0 0.01 Reference -0.05 0.05 0.30 0.0 Reference -0.10 -0.30 -0.40 -73.5 -71 -78.0 0.6007 0.6007 0.58 Max. -- 0.20 0.20 0.20 0.80 0.20 0.20 0.20 0.80 -- -- -- -- -- -- -- -- -- -- 0.3 0.3 0.4 1.2 0.3 0.3 0.5 1.2 -70 -68 -75 0.6363 0.6363 0.60 Vrms ms dB Unit
Transmit Frequency Response
Receive Frequency Response
dB
Transmit Signal to Distortion Ratio
*1
dB
Receive Signal to Distortion Ratio
*1
dB
Transmit Gain Tracking
dB
Receive Gain Tracking
dB
dBmOp
Notes:
*1 The Psophometric weighted filter is used *2 PCMIN input: idle CODE
20/41
Semiconductor AC Characteristics 1 (CODEC) (Continued)
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Symbol Freq. Level (Hz) (dBm0) tgd T1 tgd T2 tgd T3 tgd T4 tgd T5 tgd R1 tgd R2 tgd R3 tgd R4 tgd R5 CR T CR R DIS S IMD PSR T PSR R 500 600 1000 2600 2800 500 600 1000 2600 2800 1020
4.6 kHz to 72 kHz
Condition
Min. -- -- -- -- -- -- -- -- -- -- 70 75 30 -- -- 25
Typ. 0.19 0.12 0.02 0.05 0.08 0.0 0.0 0.0 0.09 0.12 78 86 32.0 -37.5 -52 30
Max. 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -- -- -- -35 -35 --
Unit
Transmit Group Delay
0
*3
ms
Receive Group Delay
0
*3
ms
Crosstalk Attenuation Discrimination Out-of-band Signal Out-of-band Signal Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio
0 -25 0 -4 50 mVpp
CAI AE CAO FHW AE BHW CAO left open 0 to 4000 Hz 4.6 kHz to 100 kHz 2fa-fb *4
dB dB dBmO dBmO dB
300 to 3400 fa = 470 fb = 320 0 to 50 kHz
Notes:
*3 The minimum value of group delay only is defined as the reference value *4 Measurement at the idle channel noise
21/41
Semiconductor AC Characteristics 2 (Transmit Path)
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Pre-Amp Gain Transmit Path Gain Transmit Path Gain Setting (VOL8) Microphone Pre-Amp Gain Microphone Pre-Amp Gain Setting (VOL9) Additional Transmit Signal Gain Symbol Freq. (Hz) GTPA GTPB1 RG1TPB RG2TPB RG3TPB GMPA RG1MPA RG2MPA GTMX 1020 1020 -- -- -- -- -4.0 -24 -- -- -- -- In-band Distortion MLDYI-TO Set at typical gain 1020 -4.0 Setting, -3 dB than -6 dB typical gain -9 dB TPAI:Terminated in 510 W Measured at TO TPAO-TPBI Directly connected Set at typical gain *5 TPAO, TO, MPAO, MPBO RL = 20 kW 1020 -24.0 1020 -24.0 Level (dBV) Condition TPAI-TPAO TPBI-TO Set at typical gain Setting, -3 dB than -6 dB typical gain -9 dB MPAI-MPAO Set at typical gain Setting, than typical gain -6 dB -9 dB Min. 18.0 15.7 -5.0 -8.0 -11.0 18.0 -8.0 -11.0 -2.0 50 -19.4 -5.0 -8.0 -11.0 -1.0 -- -4.0 -5.0 -8.0 -11.0 Typ. 20.0 17.7 -3.0 -6.0 -9.0 20.0 -6.0 -9.0 0.0 60 -17.4 -3.0 -6.0 -9.0 -- -35 -2.0 -3.0 -6.0 -9.0 Max. 22.0 19.7 -1.0 -4.0 -7.0 22.0 -4.0 -7.0 2.0 -- -15.4 -1.0 -4.0 -7.0 1.0 -30 0.0 -1.0 -4.0 -7.0 dB dB dB dBV dB % dB dB dB Unit dB dB dB dB
MPBO-TO MPAI-TO TO per wave set at typical gain Setting, -3 dB than -6 dB typical gain -9 dB
Cross Talk Attennation TMX OFF at Microphone Signal Path In-Channel PB Signal Output Level In-Channel PB Signal Output Level Setting (VOL4) In-Channel PB Signal Frequency Deviation In-Channel PB Signal Distortion Hold Tone Path Gain Hold Tone Path Gain Setting (VOL3) VPBT1 GPBT1 GPBT2 GPBT3 DfPBT THDPBT GPAT RG1PAT RG2PAT RG3PAT
Idle Channel Noise
NiTPA
--
--
--
-70
--
dBV
Maximum Output Voltage Swing
VOT
1020
--
2.4
--
--
Vpp
Note:
*5 Noise band width: 0.3 to 3.4 kHz, non weighted
22/41
Semiconductor AC Characteristics 3 (Receive Path)
MSM7503
(VDD = 5 V 5%, Ta = -10 to 70C) Parameter Symbol Freq. (Hz) GRPA RGRPA1 RGRPA2 RGRPA3 RGRPA4 RGRPA5 RGRPA6 RGRPA7 RGPAD1 RGPAD2 RGPAD3 GRMX GSIDE RGSIDE1 RGSIDE2 RGSIDE3 1020 RGSIDE4 RGSIDE5 RGSIDE6 GSP RGSP1 RGSP2 RGSP3 RGSP4 RGSP5 RGSP6 RGSP7 GSPI Level (dBV) Condition Typical gain is set between R1I and RPO -8 dB -6 dB -4 dB -2 dB 2 dB 4 dB 6 dB -3 dB -6 dB -9 dB Min. Typ. Max. Unit
Receive Signal Path Gain
-8.0 -10.0 -8.0 -6.0 -4.0 0.0 2.0 4.0 -5.0 -8.0 -11.0 -2.0 1.0 4.0 1.0 -5.0 -8.0 -11.0 -14.0 -2.0 -6.0 -10.0 -14.0 -18.0 -22.0 -26.0 -30.0 -2.0
-6.0 -8.0 -6.0 -4.0 -2.0 2.0 4.0 6.0 -3.0 -6.0 -9.0 0.0 3.0 6.0 3.0 -3.0 -6.0 -9.0 -12.0 0.0 -4.0 -8.0 -12.0 -16.0 -20.0 -24.0 -28.0 0.0
-4.0 -6.0 -4.0 -2.0 0.0 4.0 6.0 8.0 -1.0 -4.0 -7.0 2.0 5.0 8.0 5.0 -1.0 -4.0 -7.0 -10.0 2.0 -2.0 -6.0 -10.0 -14.0 -18.0 -22.0 -26.0 2.0
dB
Receive Signal Path Gain Setting (VOL1)
1020
-4.0
Setting, than typical gain
dB
Receive PAD Gain Setting (VOL10) Additional Receive Signal Path Gain Side Tone Path Gain
Setting, than typical gain 1020 -4.0
dB dB dB
R2I and RPO Typical gain is set betweenTPBI and RPO
Side Tone Path Gain Setting (VOL2) Speaker Pre-Amp Gain
Speaker Pre-Amp Gain Setting (VOL5)
1020
Additional Speaker Input Path Gain
1020
6 dB 3 dB Setting, -3 dB -14.0 than -6 dB typical gain -9 dB -12 dB Typical gain is set between RPO and SPO -4 dB -8 dB Setting, -12 dB -4.0 than -16 dB typical gain -20 dB -24 dB -28 dB Typical gain is set -4.0 between SPI and SPO
dB
dB
dB
dB
23/41
Semiconductor AC Characteristics 3 (Receive Path) (Continued)
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Additional Speaker Input Path Gain Setting (VOL6) Hold Acknowledge Tone Path Gain PB Acknowledge Tone Output Level PB Acknowledge Tone Frequency Difference PB Acknowledge Tone Distortion Incoming Tone Speaker Output Path Gain Incoming Tone Speaker Output Path Gain Setting (VOL11) Symbol Freq. (Hz) RGSPI1 RGSPI2 1020 RGSPI3 GPAR VPBRP VPBSP DfPBR THDPBR GCAO RGCAO1 RGCAO2 NiRPO -- -- 1020 -20 -- -- 1020 Level (dBV) -4.0 Condition Setting, -6 dB -12 dB than typical gain -18 dB Typical gain is set RPO per wave SPO per wave Set at typical gain RPO, SPO RPO, SPO Typical gain is set between CAO and SPO Setting, -10 dB than typical gain -20 dB R1I:SG, Measured at RPO Set at typical gain. R1I:SG, Measured at SPO Set at typical gain. R1I:SG, Gain 0 dB RMO0, RMOB *5 RPO, SPO RL = 20 kW Resister of 1.2 kW between RMO0 and RMO1 Measurement at each output Between R1I and TO Min. -8.0 -14.0 -20.0 -5.0 -32.1 -30.2 -1.0 -- -2.0 -12.0 -22.0 -- Typ. -6.0 -12.0 -18.0 -3.0 -30.1 -28.2 -- -35 0.0 -10.0 -20.0 -86.0 Max. -4.0 -10.0 -16.0 -1.0 -28.1 -26.2 1.0 -30 2.0 -8.0 -18.0 -- Unit
dB dB dBV dBV % dB dB dB
-4.0 between MLDYI and SPO
-- --
-- --
dBV
Idle Channel Noise
NiSPO
--
--
--
-89.0
--
dBV
NiRMO Maximum Output Amplitude Maximum Output Amplitude Cross Talk Attennation between Transmit Path and Receive Path VOR
-- --
-- --
-- 2.4
-86.0 --
-- --
dBV Vpp Vpp
VOR
1020
--
3.6
--
--
RX to TX
1020
-4
4.5
55
--
dBV
Note:
*5 Noise band width : 0.3 kHz to 3.4 kHz, non weighted
24/41
Semiconductor AC Characteristics 4 (Ringing Tone)
MSM7503
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter R-Tone Output Amplitude (VOL7) Symbol Condition Level Setting 1 Level Setting 2 RPO Level Setting 3 Level Setting 4 RPO SPO SPO Gain Setting -- 0 dB -10 dB -20 dB Min. 63 84 105 126 112 7.5 154 49 12 -0.5 Typ. 90 120 150 180 160 11.0 220 70 17 -- Max. 117 156 195 234 208 14.5 286 91 22 -0.5 Unit
VRTO VFTRP VFTSP VSTSP DfT
mVpp
F-Tone Output Amplitude S-Tone Output Amplitude (VOL12) Frequency Deviation
mVpp mVpp %
AC Characteristics 4 (Sounder Output Circuit)
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Symbol Freq. (Hz) VST1 VST2 VST3 VST4 ROSAO RLSAO Level (dBV) Condition Reference level of DG RLSA0 is 40 kW or more. -- Vol.1 Vol.2 Vol.3 Vol.4 Min. 3.5 1 0.25 0.2 -- 40 Typ. 4 1.2 0.44 0.27 2 -- Max. -- 1.5 0.6 0.35 -- -- Unit
Sounder Tone Output Amplitude (VOL13) Output Resistance Output Load
--
--
V kW kW
With respect to DG
LCD Defelection Angle Control Voltage Output
(VDD = 5 V 5%, Ta = -10C to 70C) Parameter Symbol Condition DB2 DB1 DB0 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 -- To GND Min. 1.1 0.9 0.7 0.5 0.3 0.2 0.15 0.0 -- 100 Typ. 1.4 1.2 1.0 0.8 0.8 0.4 0.2 0.0 1.0 -- Max. 1.7 1.5 1.3 1.1 0.9 0.6 0.4 0.05 -- -- Unit
Output Voltage
VLCD
V
Output Resistance Output Load
ROLCD RLLCD
kW kW
25/41
Semiconductor
MSM7503
TIMING DIAGRAM
Reset Signal Output Timing
VD (VA) LRSTN (a) LRSTN output timing by the power supply voltage charging Writing the reset data of WDT Internal WDT output tdRST3 LRSTN tWRST (b) LRSTN output timing by the internal WDT TWDT TWDT Vth tdRST1 Vtl tdRST2 Vth tdRST1
Figure 1
Processor Interface Timing
AD0, AD1 tAW1 CEN tCW1 WRN RDN tW tDW1 tDW2 DB0 to DB7 tPDSCN PO0 to PO7 tPDLA Latch Output tPDDATA tCW2 tCR1 tR tCR2 tAW2 tAR1 tAR2
tPDDATA
Figure 2
26/41
Semiconductor B-bit signal I/O Timing
MSM7503
1/fSYNC TWSYNC SYNC 1/fCLK1 CLK1 tdFHW tdSCK1

FHW Output F0 F1 F2 F3 F4 F5 F6 F7 F0 F1 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 BHW Input TSBHW THBHW
Figure 3
D-, K-bit Signal I/O Timing
SYNC
1/fCLK2
tdSCK2
CLK2
1/fCLK3
tdSCK3
CLK3 (CLC=1) CLK3 (CLC=0)
tdFD
tdFD
FD Output
BD Output
TSBD
tdFK
THBD
FK Output
Figure 4
27/41
Semiconductor
Ping-Pong Transmission Signal Timing
1 Frame (TFM 125 ms) Wave Shape of Line Signal R1N TWB
1
Receive (62.4 ms)
Transmit (50.78 ms)
Receive
, , , , , ,
R2N TCB
1
Receive Data SYNC CLK1
1
1
K
D
B
DC
FP
K
D
B
125 ms
FHW
RB1
RB2
BHW
TB8
CLK2 CLK3
FD
RD1
BD FK
TD1
TD2
RK
T1N Transmit T2N
tWF
MSM7503
Transmit Data
1
1
D
B
DC
28/41
Figure 5
Semiconductor
FUNCTIONAL DESCRIPTION
Control Data Description Sounder Calling Tone and tone ON/OFF control WRITE Mode Address Data
AD1 = 0, AD0 = 0
Control Data Description for Control Sounder output ON Sounder output OFF Sounder output ON Sounder output OFF R-Tone R-Tone F-Tone F-Tone F-Tone F-Tone ON OFF ON(1 kHz) OFF ON(1 kHz) OFF SW19 ON SW19 OFF SW20 ON SW20 OFF SW13 ON SW13 OFF SW14 ON, SW14 OFF, SW14 OFF, SW14 OFF, SW15 OFF, SW15 OFF, SW15 ON, SW15 OFF, Tone Output: SPO Tone Output: RPO Tone Output: SPO *1 Remarks Tone Output: SA0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1
*1: This Sounder Output is sent at the timing shown below.
ON
OFF
ON
OFF
0.625 s 0.25 s 0.125 s
2s
MSM7503
29/41
Semiconductor
Level and frequency control of sounder and R-tone WRITE Mode Address Data
AD1 = 0, AD0 = 0
Control Data Description for Control SA0 output sounder volume 1 (Large) SA0 output sounder volume 2 (Middle) SA0 output sounder volume 3 (Small 1) Remarks Sounder volume and tone are defind at a time.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 -- -- -- 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 -- 0 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 -- 0 1 0 1 -- 0 1 0 1
At the initial setting, sounder volume 1 and sounder SA0 output sounder volume 4 (Small 2) combination tone 1 are set. Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz) SA0 sounder volume: Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz) VOL 13 Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz) Sounder combination tone 4 (Single tone of 1000 Hz) Sounder combination tone 5 (Single tone of 800 Hz) Sounder combination tone 6 (Single tone of 400 Hz) R-Tone output level 1 (90 mVPP at RPO output) R-Tone output level 2 (120 mVPP at RPO output) R-Tone output level 3 (150 mVPP at RPO output) R-Tone output level 4 (180 mVPP at RPO output) R-Tone 400 Hz single tone R-Tone 425 Hz single tone R-Tone 440 Hz single tone R-Tone 450 Hz single tone R-Tone 400 Hz ON/OFF by 16 Hz R-Tone 400 Hz ON/OFF by 20 Hz R-Tone output level and frequency are defined at a time. At the initial setting, output level 1 and a single 400 Hz tone are set. R-Tone output level = VOL 7
MSM7503
30/41
Semiconductor
PB tone control WRITE Mode Address Data
AD1 = 0, AD0 = 0
Control Data 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X Output PB Frequency Low 697 Hz 697 697 697 770 770 770 770 852 852 852 852 941 941 941 941 High 1209 Hz 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633 1209 1336 1477 1633 SW16, SW17, SW18: OFF When PBTC = 1 SW16: OFF SW17: OFF SW18: ON PB tone is sent to the receive path SPO only. When PBTC = 0 SW16: ON SW17: ON SW18: OFF PB tone is sent to the transmit path T0 and the receive path RPO. 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB
1
0
1
PBTC
0 1 1 1 1 1 1 1 1
0
0
X
PB tone stop
MSM7503
31/41
Semiconductor
SW control and timer reset WRITE Mode Address Data
AD1 = 0, AD0 = 0
Control Data Description for Control SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12 LA = 1 LB = 1 ON ON ON ON ON ON ON ON ON ON ON ON Transmit handfree input Transmit handset input Receive input Side tone input Receive main amplifier input Receive speaker input Transmit path hold tone input Receive path hold tone Acknowledge input Additional receive input Additional speaker input Speaker DEC input PCM output enable General Latch output for external control Remarks When hold tone or PB tone transmit is selected, these inputs are muted. -- When Handfree input is selected, side tone is muted. -- -- -- Speaker DEC input = CODEC AOUT --
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0
Above codes
Above corresponding SW or latch is set to OFF or "0". All of above SWs or latches are set to OFF or "0" at the initial setting stage. Watchdog timer is reset.
MSM7503
32/41
Semiconductor
Gain setting (receive gain, side tone gain) WRITE Mode Address Data
AD1 = 0, AD0 = 0
Control Data Description for Control Typical receive gain (-6dB) -8 dB than the typical gain -6 dB than the typical gain -4 dB than the typical gain -2 dB than the typical gain +2 dB than the typical gain +4 dB than the typical gain +6 dB than the typical gain Typical side tone gain (-9 dB) -12 dB than the typical gain -9 dB than the typical gain -- -6 dB than the typical gain -3 dB than the typical gain +3 dB than the typical gain +6 dB than the typical gain Side tone OFF (VOL2 max loss) Receive gain and side tone gain are set at a time. At the initial setting, the typical gain is set. Remarks Receive gain = VOL1 Side tone gain = VOL2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 -- -- -- 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
MSM7503
33/41
Semiconductor
Gain control (transmit hold tone, PB tone, microphone input, handset input) WRITE Mode Address Data
AD1 = 0, AD0 = 1
Control Data Description for Control Typical transmit hold tone gain (-2 dB) -3 dB with respect to the typical gain -6 dB with respect to the typical gain -9 dB with respect to the typical gain Typical transmit PB tone gain (+4 dB) -- -3 dB with respect to the typical gain -6 dB with respect to the typical gain -9 dB with respect to the typical gain 0 -- 1 0 0 1 1 0 1 0 1 -- -- 0 1 1 0 1 0 1 Typical handfree input gain (+20 dB) -6 dB with respect to the typical gain -9 dB with respect to the typical gain -- Typical handset input gain (+12 dB) -3 dB with respect to the typical gain -6 dB with respect to the typical gain -9 dB with respect to the typical gain Handfree input gain = VOL9 Handset input gain = VOL8 Handfree input gain and handset Input gain are set at a time. At the initial setting, the typical gain is set. Remarks Transmit hold tone gain = VOL3 Transmit PB tone gain = VOL4 Hold tone gain and PB tone gain are set at a time. At the initial setting, the typical gain is set.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 -- 0 0 0 1 0 1 0 1 0 1 0 1 -- 0 1 1 0 1 0 1
MSM7503
34/41
Semiconductor
Gain control (receive PAD, speaker) WRITE Mode Address Data
AD1 = 0, AD0 = 1
Control Data Description for Control Typical speaker pre-amp. gain (0 dB) -4 dB with respect to the typical gain -8 dB with respect to the typical gain -12 dB with respect to the typical gain -16 dB with respect to the typical gain -20 dB with respect to the typical gain -24 dB with respect to the typical gain -28 dB with respect to the typical gain Typical additional speaker input path gain (0 dB) -- -6 dB with respect to the typical gain -12 dB with respect to the typical gain -18 dB with respect to the typical gain 0 0 0 -- 0 1 1 0 1 0 -- 0 1 0 1 0 1 Speaker receive OFF(SW21 OFF) Speaker receive ON (SW21 ON) Typical receive PAD gain (0 dB) -3 dB with respect to the typical gain -6 dB with respect to the typical gain -9 dB with respect to the typical gain Typical incoming tone gain (0 dB) -10 dB with respect to the typical gain -20 dB with respect to the typical gain Receive PAD = VOL10 Incoming tone gain = VOL11, VOL12 Receive PAD and incoming tone gain are set at a time. At the initial setting, the typical gain is set. At the initial setting, SW21-OFF and the typical gain are set. Remarks Speaker pre-amp. gain = VOL5 Additional speaker gain = VOL6 Speaker pre-amp. gain and additional speaker gain are set at a time.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 -- 1 1 0 0 0 1 1 0 0 0 1 0 1 0 -- 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
1
1
0
0 0 0 1
MSM7503
35/41
Semiconductor
Key scanning signal output control WRITE Mode Address Data
AD1 = 1, AD0 = 0
Controlo Data Description for Control The data set on DB7 to DB0 are output on PO7 to PO0 respectively. Output data is held until next data is written. When the set data is set to "0", output data goes to "0", when set to "1", output pin is left open. At the initial setting, PO7 to PO0 are in open state.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Output Data
Key scanning data read out Read Mode Address Data
AD1 = 1, AD0 = 0
Contorol Data Description for Control PI2 PI1 PI0 Data input onto PI7 to PI0 are output onto DB7 to DB0.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PI7 PI6 PI5 PI4 PI3
MSM7503
36/41
Semiconductor
Special functions WRITE Mode Address Data
AD1 = 1, AD0 = 1
Contorol Data Description for Control Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD Deflection Angle Control Voltage Output 0 0 0 0 1 0 0 0 0 1 1 1 1 Power Down Mode Control 0 1 0 0 0 0 0 0 1 1 CODEC Control -- 1 1 0 0 0 0 0 1 *2: 0 1 -- 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
VLCD pin output voltage: 0.0 V : 0.20 V : 0.40 V : 0.60 V : 0.8 V : 1.0 V : 1.2 V : 1.4 V Analog, CODEC power down mode Analog, CODEC power ON mode CODEC power down mode CODEC power ON mode CODEC operates in m-law CODEC operates in A-law FHW and BHW are normally connected BHW is connected to FHW At the initial setting stage, set to analog and CODEC power down mode. CODEC power ON/OFF control is valid in the analog and CODEC power ON mode. At the initial setting stage, set to m-law, and FHW and BHW are normally connected. The componding law and the connection control are set at a time. At the initial setting stage, set to 0 V.
Even during the analog and CODEC power down mode, following functions are available, Key scanning data I/O, sounder outputs (SA0), WDT, and general latch output (LA, LB)
MSM7503
37/41
MIC Input 100 kW 0.1 mF +5 V R1N MLDYI Hold Tone Generator 100 kW
*1
+5 V TPBI MPAO MPBI MPBO 0.1 mF TO CAI
100 kW
MPAI
TPAO
SGT +5 V R2N
Semiconductor
Line
APPLICATION CIRCUIT
100 kW
TPAI CAO
R1I RPO T1N
+5 V
Handset
RMI T2N +5 V
*2
RMO0
RMO1
SPO
SPI
Speaker
SAO
Controller
PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7
PPPPPPPP IIIIIIII 01234567
S G C
C T E ADS GGT
T E SVV T D A X1
X2
FD
PS LRSTN WRN RDN CEN DB0 to DB7 AD0 AD1 CLK2 CLK3 BD BDS CLC FK
*1 Inserting a capacitor (1 to 22 mF) between SGT and AG will inprove the transmit path noise characteristics
0.1 mF
0-10 W 0.1 mF to 1 mF + 10 mF
+5 V
*2 Insert a resistor if necessary
SW Matrix
0V
MSM7503
38/41
MSM7503 Speech Path Level Setting
Semiconductor
TPAO TPBI MPAI MPAO TPAI
+
MLDYI MPBI MPBO SW1 SW2 SW7 SW16 0 dB 5.7 dB VOL 3 VOL 4
-
TO
CAI
VOL 9
+
20 dB
- -20 dB to +25 dB
+
AIN CODEC AOUT
VOL 8 CAO R1I R2I RPO RMI SW5 RMO0 0 dB RMO1
- - -
VOL 10
-
0 dB VOL 1 VOL 2 VOL 7
-8.7 dB
SW9 SW3 SW4 SW13 SW17 SW14 SW6 SW8 SW18 SW10
PB GEN. Per Wave 0.24 VPP(-21.4 dBV Equivalent) R-Tone GEN. 90 mVPP Pulse (-27.8 dBV Equivalent) F-Tone GEN. 0.16 VPP Pulse (-22.8 dBV Equivalent) S-Tone GEN. 0.22 VPP Pulse (-20.0 dBV Equivalent)
CODEC I/O Level Overload Point: 1.2 Vop 0 dBmO : 0.6007 Vrms (-4.4 dBV)
SW5
0 dB 0 dB
VOL No. Typical Level Variable Range
VOL 1 VOL 2 VOL 3 VOL 4 VOL 5 VOL 6 VOL 7 VOL 8 VOL 9 VOL 10 VOL 11 VOL 12 -6 dB -9 dB -2 dB +4 dB 0 dB 0 dB 0 dB +12 dB +20 dB 0 dB 0 dB 0 dB -14 dB to 0 dB -21 dB to -3 dB -11 dB to -2 dB -5 dB to +4 dB -28 dB to 0 dB -18 dB to 0 dB 90 mV to 180 mV +3 dB to +12 dB +11 dB to +20 dB -9 dB to 0 dB -20 dB to 0 dB -20 dB to 0 dB
Step Width
2 dB 3 dB 3 dB 3 dB 4 dB 6 dB 30 mV 3 dB 3,6 dB 3 dB 10 dB 10 dB
SPO
-
VOL 5 VOL 12 VOL 11
-22 dB
SW21 SW20 SW11 SW15
-
-3 dB -6.8 dB
VOL 6
SPI
Note :
+
: The output signal is input with the same phase as : The output signal is with inverted phase.
MSM7503
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-
Semiconductor
MSM7503
RECOMMENDATIONS FOR ACTUAL DESIGN
* To assure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the VA and AG pins. * Connect the AG pin and the DG pin each other as close as possible. Connected to the system ground with low impedance. If the AG and DG of the device are connected to different ground lines, the device may be latched up. * Connect the VA pin and the VD pin as close together as possible and routed them to the analog 5 V power supply. If the VA and VD of the device are connected to different power supplies, the device may be latched up. * Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an IC socket is unavoidable, the short lead type socket is recommended. * When mounted on a frame, electro-magnetic shielding should be recommended, if any electromagnetic wave source such as power supply transformers is surrounding the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply should be used to avoid the erroneous operation and the degradation of the characteristics of these devices. * Connect analog input pins and digital input pins that are not used to the SG pin and to GND, respectively. * When the data is written differently from the data defined in the section, Control Data Description in Functional Description, the device is not guaranteed in normal operation.
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Semiconductor
MSM7503
PACKAGE DIMENSIONS
(Unit : mm) QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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